1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a test structure in which a sequence of conductors are spaced by an increasing distance from a respective sequence of gate conductors. The test structure may be used to determine how lithographic patterning of the gate conductors laterally spaced from the conductors affects the operation of transistors employing the gate conductors.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
An integrated circuit typically includes multiple isolated devices arranged upon and within a unitary substrate. Various devices are electrically linked together with interconnect routing residing above and extending between contacts that have been formed through an interlevel dielectric to the devices. As such, the gate conductor of a MOSFET device is commonly formed coaxial to and isolated from another conductor which is to be employed by a separate device, e.g. a capacitor. FIGS. 1-3 illustrate the simultaneous formation of a gate conductor and a conductor which are laterally spaced apart and extend along the same axis. As shown in FIG. 1, a semiconductor substrate 2 is provided within which a trench isolation structure 4 has been formed. A gate dielectric 6 is arranged across the upper surface of substrate 2. A potentially conductive material 8 (e.g., polysilicon that may be subsequently rendered conductive with dopants), is shown deposited across gate dielectric 6. Also, a photosensitive material, i.e., photoresist 10 has been spin-on deposited across the upper surface of substrate 2.
FIG. 2 demonstrates a partially transparent mask plate 12 which may be used to pattern photoresist 10 using a well-known technique known as "lithography". Mask plate 12 includes transparent region 13 and non-transparent regions 14. The sizes and shapes of non-transparent regions 14 are equivalent to the sizes and shapes of the ensuing gate conductor and conductor which are to be formed from conductive material 8. The configuration of transparent region 13 with respect to non-transparent regions 14 is applicable when photoresist 10 is a positive photoresist. However, if photoresist 10 is a negative photoresist, transparent region 13 and non-transparent regions 14 would need to be reversed such that region 13 is non-transparent and region 14 is transparent. Mask plate 12 may be placed a relatively small spaced distance above photoresist 10 during the lithography process. Patterns upon mask plate 12 are projected upon photoresist 10 using a form of radiation, e.g., ultraviolet light. The radiation is transmitted exclusively through transparent portion 13 of mask plate 12 to photoresist 10, transferring an optical image to photoresist 10.
Diffraction effects may undesirably occur as the radiation passes through the slit-like area 15 of transparent region 13 interposed between the two non-transparent regions 14. As a result, the radiation projected onto photoresist 10 may have an intensity distribution of light and dark bands. It is well known that a series of slits which, when irradiated with coherent light, will emit diffraction patterns which interfere with each other to produce an intensity pattern of light over a wide range of diffraction orders, n. Unfortunately, only a small number of the lower orders of light are able to pass through the lens system of the exposure tool used to project the radiation to mask plate 12. Absent the higher orders of light, the image projected onto photoresist 10 may lack some of the characteristics of the original mask pattern. In particular, sharp comers in the mask pattern may be lost, resulting in a projected image with rounded comers. Further, the length of the projected image may be shorter than that of the original mask pattern.
The solubility of the region of positive photoresist 10 exposed to the radiation is altered by a photochemical reaction and thus may be washed away with a solvent to form a photoresist pattern like that of the projected image. Alternately, if a negative photoresist 10 is used, those regions of photoresist 10 exposed to the radiation are retained while the unexposed region is washed away. Subsequently, the now-patterned photoresist 10 is exposed to an etchant that removes those portions of conductive material 8 and gate dielectric 6 unprotected (i.e., not covered) by the photoresist 10. In this manner, a conductor 16 is formed a spaced distance from a gate conductor 18, as shown in FIG. 3. Dashed lines 17 represent where conductor 17 and gate conductor 18 would have been located had there been no damaging diffraction effects during the exposure of photoresist 10. However, since the photoresist pattern is dissimilar from the original mask pattern, conductor 16 and gate conductor 18 are not shaped and sized exactly as they would have been if no diffraction effects had occurred. Consequently, instead of having well-defined corners, the ends of conductor 16 and gate conductor 18 become more curved as the spacing between the conductors decreases. Further, the lengths of conductor 16 and gate conductor 18 which extend along the same axis 23 are reduced relative to their corresponding patterns in mask plate 12.
In subsequent processing steps, impurity dopants may be implanted into source and drain regions 19 of substrate 10 which are bounded by an isolation region 4. Gate conductor 18 serves as a masking layer during the source/drain implant so that dopant species are inhibited from being implanted into the channel region of substrate 10 underlying gate conductor 18. Since the gate length of gate conductor 18 may become shorter than its design specification, gate conductor 18 might not extend across the entire length of source and drain regions 19. Therefore, source and drain regions 19 undesirably communicate with each other between the end of shortened gate conductor 18 and isolation region 4. Unfortunately, due to the shortening of gate conductor 18 and the rounding of the comers of gate conductor 18, a subthreshold current may inadvertently flow between source and drain regions 19 when the transistor is in its off state. The rounding of the comers of the gate conductor 18 contribute to the current leakage between source and drain regions 19 by reducing the distance between those regions. While a gate conductor patterned a spaced distance from another conductor might not be shortened to the extent shown in FIG. 3, even a small amount of shortening might lead to some current leakage between adjacent source and drain regions. Moreover, the drive current of an operating transistor in which the gate conductor has rounded edges and hence a reduced gate width might fluctuate from design specification. As the device dimensions and the spacing between device dimensions have continuously been reduced, the distance by which a gate conductor extends beyond the source and drain regions has also been decreased. Consequently, it has become more probable that gate conductor shortening and rounding of the gate conductor corners will result in current leakage between adjacent source and drain regions.
It would therefore be of benefit to determine the effect that lithographic patterning of a gate conductor spaced from a conductor of similar material has on the properties of the transistor which employs the gate conductor. A test structure and method must be developed for comparing the properties of transistors having gate conductors lithographically patterned varying distances from other conductors. Such a test structure would allow one to determine the spacing required between a gate conductor and another conductor to significantly reduce current leakage between source and drain regions adjacent to the gate conductor. Further, a test structure is needed which could be used to determine how far the gate conductor must extend beyond the source and drain regions to provide sufficient protection against current leakage. Such a test structure would also allow one to characterize the relationship between the rounding and shortening of a gate conductor of a transistor and electrical properties resulting from that transistor.